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Ordering number : ENN6237
CMOS IC
LC895198
CD-ROM Decoder for 32x ATAPI (IDE) Drives
Overview
The LC895198 is a CD-ROM decoder that supports ATAPI (IDE) and includes 1 MB of on-chip DRAM.
Functions
* * * * * * CD-ROM ECC function Sub-code read function Built-in ATAPI (IDE) I/F (register and other blocks) CAV audio function Built-in DVD-ROM I/F (8-bit width) Built-in 1-Mbit DRAM
* Built-in CAV-AUDIO function * Built-in intelligent functions (auto buffering, auto decoding, CD-R support, etc.) * Built-in subcode P to W buffering function (NO-ECC) and CD-TEXT support
Package Dimensions
unit: mm 3237-LQFP120
[LC895198]
16.0 14.0 (1.2) 0.4 0.125
Features
* 32x speed supported 16.6MBytes/s (with IORDY) Operation frequency: 33.8688 MHz * 32x speed supported 16.6MBytes/s (without IORDY) Operation frequency: 36 MHz * CD main channel, C2 flag, and subcode areas in buffer RAM can be set freely by user * Built-in batch transfer function (function for sending CD main channel, C2 flag, subcode, etc., at one time) * Built-in multi transfer function (function for sending several blocks at one time)
16.0
14.0 0.4
120
(1.2)
1
0.15
(1.4)
0.1
1.6max
0.5
(0.5)
SANYO: LQFP120
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage Input/output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature (pin part only) Input/output power II, IO Symbol VDD max VI, VO Pd max Topr Tstg 10 s Per 1 input/output reference cell Ta = 25C Ta = 25C Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 400 0 to +70 -55 to +125 235 20 Unit V V mW C C C mA
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N3099TH (OT) No. 6237-1/10
LC895198 Allowable Operating Ranges at Ta = 0 to +70C, VSS = 0 V IO cell 5.0 V supply voltage
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
Internal cell 3.3 V supply voltage
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 3.0 0 typ 3.3 max 3.6 VDD Unit V V
Electrical Characteristics at Ta = 0 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Output low-level voltage Input leak current Output leak current Pull-up resistance Pull-down resistance The applicable pin sets are as follows. INPUT (1) (2) (3) ATPINSEL, CSCTRL, SUA0 to SUA6, BCK, C2PO, LRCK, DSDATA, SBS0, SCOR, WFCK, TEST0 to TEST1, AUDIOCK ZRESET, ZCS, ZRD, ZWR, CSEL DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST Symbol VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL VOL VOL IIL IOZ RUP RDN DRESP, DREQ, HDB0 to HDB7 Conditions Applicable pins Ratings min 2.2 -- 2.2 -- 2.2 -- 2.4 -- VDD - 2.1 -- VDD - 2.1 -- VDD - 2.1 -- -- -- -10 -10 40 40 80 80 typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- max -- 0.8 -- 0.8 -- 0.8 -- 0.8 -- 0.4 -- 0.4 -- 0.4 0.4 0.4 +10 +10 160 160 Unit V V V V V V V V V V V V V V V V A A k k
TTL levels TTL levels with pull-up resistor TTL levels Schmitt with pull-down resistor TTL levels Schmitt IOH = -2 mA IOL = 2 mA IOH = -8 mA IOL = 8 mA IOH = -4 mA IOL = 24 mA IOL = 24 mA IOL = 8 mA VI = VSS, VDD During high-impedance output
(1)
(9) DRESP HDB0 to HDB7 (2), (3), (10)
(9)
(4)
(7), (10) (8) (5), (6) (1), (2), (3), (10) (5), (7), (8), (10) (6), (9)
OUTPUT (4) (5) (6) (7) (8) EXCK, DREQ, MCK, MCK3 ZRSTCPU ZINT, ZINT1, ZSWAIT DMARQ, HINTRQ IORDY, ZIOCS16
INOUT (9) D0 to D7 (10) DD0 to DD15, ZDASP, ZPDIAG Note: Pins other than XTAL and XTALCK are not included in DC characteristics.
No. 6237-2/10
LC895198 Recommended Oscillator Circuit Example LC895198
XTALCK PN28
R1
XTAL PN29 R2
C1
C2
A12524
R1 = 1 M R2 = 15 C1 = 0 C2 = 47 pF When the ceramic clock oscillator frequency is 33.8688 MHz: (The 33.8688 MHz in this recommended example is the third harmonic.) The exact values of the components are influenced by the printed circuit board used. Consult with the manufacturer of the oscillator element used to determine these values.
No. 6237-3/10
LC895198 Block Diagram
Data bus[0:7] *1 EXCK
RAM Data bus[0:15] Address bus[0:16]
LC895198
Sub-code I/F 10byte FIFO for Sub Q Address generator
CAV-Audio contorol CD-DSP Address generator
*10
DAC
*2
CD-DSP I/F & SYNC Detector
De-scramble & Buffering Address generator
ECC & EDC ZRESET ZRSTCPU HOST *3 *4 *5 ZINT0 ZINT1 *6 *7 ZSWAIT Each Block XTALCK XTAL DVD-ECC dec MCK3 MCK *8 *9 Clock generator Each Block Register R0-R127 decoder Reset Controller Address generator Each Block Bus control signal 1Mbit IDE I/F Based HISIDE **1 Bus Arbiter & DRAM controller
Buffer
DRAM Data output input I/F Address generator
Micro controller
Microcontroller RAM access Address generator
DVD-ECC I/F Address generator
A12525
*1 *2 *3 *4 *5 *6 *7 *8 *9 *10 **1
WFCK, SBSO, SCOR BCK, SDATA, LRCK, C2PO DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, CSEL DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL D0 to D7 HDB0 to HDB7, DRESP DREQ DBCK, DLRCK, DSDATA HISIDE(WD25C32) is made by WESTERN DIGITAL
No. 6237-4/10
LC895198 Pin Functions LC895198 Pin Functions 1 (When ATPINSEL (pin 113) is 0)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin VDD0 DREQ DRESP HDB7 (IOP0) HDB6 (IOP1) HDB5 (IOP2) HDB4 (IOP3) HDB3 (IOP4) HDB2 (IOP5) HDB1 (IOP6) HDB0 (IOP7) MCK3 VSS0 VDD1 VDD0 DSDATA DLRCK DBCK C2PO SDATA BCK LRCK EXCK WFCK SBSO SCOR MCK XTALCK XTAL VSS0 VDD1 VDD0 VSS0 CSCTRL ZRD ZWR ZCS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VDD1 VDD0 VSS0 Type P O I B B B B B B B B O P P P O O O I I I I O I I I O I O P P P P I I I I I I I I I I I P P P 3.3 V 5.0 V Microcontroller register selection signals Active low/active high selection for the microcontroller CS pin Microcontroller data read signal input Microcontroller data write signal input Register chip select input from the microcontroller 3.3 V 5.0 V XTALCLK 1/1, 1/2, and stop output Crystal oscillator circuit input Crystal oscillator circuit output Subcode I/O CD DSP interface D/A converter output 3.3 V 5.0 V XTALCLK 1/1, 1/2, and stop output DVD ECC data I/O These pins can be switched to function as general-purpose I/O ports by register settings. 5.0 V DVD ECC data request output DVD ECC data latch signal input I O INPUT OUTPUT B P Function Type BIDIRECTION POWER NC NOT CONNECT
Continued on next page.
No. 6237-5/10
LC895198
Continued from preceding page.
Pin No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin D0 D1 D2 D3 D4 D5 D6 D7 ZINT0 ZINT1 ZSWAIT ZRSTCPU VSS0 VDD0 CSEL ZHRST ZDASP ZCS3FX ZCS1FX VSS1 DA2 DA0 ZPDIAG DA1 VSS1 ZIOCS16 HINTRQ VSS1 VDD1 ZDMACK IORDY VSS1 ZDIOR ZDIOW DMARQ DD15 DD0 VSS1 DD14 DD1 DD13 DD2 VSS1 VDD0 DD12 DD3 DD11 DD4 VSS1 DD10 DD5 DD9 VSS1 Type B B B B B B B B O O O O P P I I B I I P I I B I P O O P P I O P I I O B B P B B B B P P B B B B P B B B P ATAPI data bus ATAPI data bus 5.0 V ATAPI data bus ATAPI data bus ATAPI control signals 3.3 V ATAPI control signals ATAPI control signals ATAPI control signals ATAPI control signals 5.0 V Interrupt request signal output to the microcontroller WAIT signal output to the microcontroller CPU reset signal output Microcontroller data signals. These pins have built-in pull-up resistors. Function
Continued on next page.
No. 6237-6/10
LC895198
Continued from preceding page.
Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin DD6 DD8 DD7 VDD1 VDD1 VDD0 VDD1 ZRESET VDD1 VSS0 TEST1 VSS0 ATPINSEL VSS0 TEST0 VDD0 AUDIOCK VDD0 VDD0 VSS0 Type B B B P P P P I P P I P I P I I I P P P Test pin. This pin must be connected to VSS in normal operation. 5.0 V Clock input for the CAV audio block 5.0 V 5.0 V ATAPI pin layout selection. This pin must be connected to VSS0. Test pin. This pin must be connected to VSS in normal operation. 3.3 V 3.3 V 5.0 V 3.3 V IC reset input 3.3 V ATAPI data bus Function
* Unused ("NC") pins must be left open. * Pins whose name begin with a Z operate with inverted (negative) logic. * VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. * Applications must supply 5.0 V to VDD0 and 3.3 V to VDD1.
No. 6237-7/10
LC895198 Pin Functions LC895198 Pin Functions 2 (When ATPINSEL (pin 113) is 1)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin VDD0 DREQ DRESP HDB7 (IOP0) HDB6 (IOP1) HDB5 (IOP2) HDB4 (IOP3) HDB3 (IOP4) HDB2 (IOP5) HDB1 (IOP6) HDB0 (IOP7) MCK3 VSS0 VDD1 VDD0 DSDATA DLRCK DBCK C2PO SDATA BCK LRCK EXCK WFCK SBSO SCOR MCK XTALCK XTAL VSS0 VDD1 VDD0 VSS0 CSCTRL ZRD ZWR ZCS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VDD1 VDD0 VSS0 Type P O I B B B B B B B B O P P P O O O I I I I O I I I O I O P P P P I I I I I I I I I I I P P P 3.3 V 5.0 V Microcontroller register selection signals Active low/active high selection for the microcontroller CS pin Microcontroller data read signal input Microcontroller data write signal input Register chip select input from the microcontroller 3.3 V 5.0 V XTALCLK 1/1, 1/2, and stop output Crystal oscillator circuit input Crystal oscillator circuit output Subcode I/O CD DSP interface DAC converter output 3.3 V 5.0 V XTALCLK 1/1, 2/5, 1/5, 1/512, and stop output DVD ECC data I/O These pins can be switched to function as general-purpose I/O ports by register settings. 5.0 V DVD ECC data request output DVD ECC data latch signal input I O INPUT OUTPUT B P Function Type BIDIRECTION POWER NC NOT CONNECT
Continued on next page.
No. 6237-8/10
LC895198
Continued from preceding page.
Pin No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin D0 D1 D2 D3 D4 D5 D6 D7 ZINT0 ZINT1 ZSWAIT ZRSTCPU VSS0 VDD0 CSEL DD7 DD8 DD6 DD9 VSS1 DD5 DD10 DD4 DD11 VSS1 DD3 DD12 VSS1 VDD1 DD2 DD13 VSS1 DD1 DD14 DD0 DD15 DMARQ VSS1 ZDIOW ZDIOR IORDY ZDMACK VSS1 VDD0 HINTRQ ZIOCS16 DA1 ZPDIAG VSS1 DA0 DA2 ZCS1FX VSS1 Type B B B B B B B B O O O O P P I B B B B P B B B B P B B P P B B P B B B B O P I I O I P P O O I B P I I I P ATAPI control signal ATAPI control signal 5.0 V ATAPI control signal ATAPI control signal ATAPI data bus 3.3 V ATAPI data bus ATAPI data bus ATAPI data bus ATAPI control signals ATAPI data bus 5.0 V Interrupt request signal output to the microcontroller WAIT signal output to the microcontroller CPU reset signal output Microcontroller data signals. These pins have built-in pull-up resistors. Function
Continued on next page.
No. 6237-9/10
LC895198
Continued from preceding page.
Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin ZCS3FX ZDASP ZHRST VDD1 VDD1 VDD0 VDD1 ZRESET VDD1 VSS0 TEST1 VSS0 ATPINSEL VSS0 TEST0 VDD0 AUDIOCK VDD0 VDD0 VSS0 Type I B I P P P P I P P I P I P I I I P P P Test pin. This pin must be connected to VSS in normal operation. 5.0 V Clock input for the CAV audio block 5.0 V 5.0 V ATAPI pin layout selection. This pin must be connected to VDD0. Test pin. This pin must be connected to VSS in normal operation. 3.3 V 3.3 V 5.0 V 3.3 V IC reset input 3.3 V ATAPI control signal Function
* Unused ("NC") pins must be left open. * Pins whose name begin with a Z operate with inverted (negative) logic. * VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. * Applications must supply 5.0 V to VDD0 and 3.3 V to VDD1.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 1999. Specifications and information herein are subject to change without notice. PS No. 6237-10/10

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